The present invention relates to an address/display separation system AC-type plasma display apparatus (PDP apparatus) used as a display unit of a personal computer or work station, a flat TV, or a plasma display for displaying advertisements, information, etc.
For an AC-type color PDP apparatus, an address/display separation system is widely employed, in which a period (an address period) during which cells to be used for display are selected and a display period (a sustain period) during which a discharge is caused to occur for light emission to produce a display are separated. In this system, charges are accumulated in the cells to be lit during the address period and a discharge is caused to occur for producing a display during the sustain period by the use of the charges.
PDP apparatuses include: a two-electrode type apparatus in which a plurality of first electrodes extending in a first direction are provided in parallel to each other and a plurality of second electrodes extending in a second direction perpendicular to the first direction are provided in parallel to each other; and a three-electrode type apparatus in which a plurality of first electrodes and a plurality of second electrodes each extending in a first direction are provided by turns in parallel to each other and a plurality of third electrodes extending in a second direction perpendicular to the first direction are provided in parallel to each other. Recently, the three-electrode type PDP has been widely used. The present invention can be applied not only to the two-electrode type PDP apparatus but also to the three-electrode type PDP apparatus. First, the three-electrode type PDP apparatus is taken as an example for an explanation here.
FIG. 1 is an exploded perspective view showing an example of a structure of a three-electrode type plasma display panel (PDP). As shown schematically, on a front substrate 1, X electrodes (first electrodes) 11 and Y electrodes (second electrodes) 12 between which a sustain discharge is caused to occur are arranged by turns in parallel to each other. These groups of electrodes are covered with a dielectric layer 13 and the surface thereof is further covered with a protective layer 14 such as MgO. On a back substrate 2, address electrodes 15 extending in a direction substantially perpendicular to the X electrodes 11 and the Y electrodes 12 are arranged and these electrodes are further covered with a dielectric layer 16. At both sides of the address electrodes 15, partitions 17 are arranged, defining the cells in the direction of column. Moreover, the dielectric layer 16 and the sides of the partitions 17 on the address electrodes 15 are coated with phosphors 18, 19 and 20 that are excited by ultraviolet rays to generate red (R), green (G) and blue (B) visible light. The front substrate 1 and the back substrate 2 are bonded together so that the protective layer 14 comes into contact with the partitions 17 and a discharge gas composed of neon (Ne), xenon (Xe), etc., is enclosed, and thus a panel is constructed.
In this structure, the X electrode 11 and the Y electrode 12 are each made of a bus electrode formed by a metal layer and a transparent electrode, and are arranged so that the transparent electrodes of a pair of the X electrode 11 and the Y electrode 12 are close to each other. A display cell is defined at the intersection of a pair of the X electrode 11 and the Y electrode 12 and the address electrode 15.
It is difficult for a plasma display panel to produce a gradated display by controlling the discharge intensity, therefore, one image (one frame: 1/60 sec) is made up of a plurality of subfields and a gradated display is produced by combining subfields to be lit for each cell. FIG. 2 is a diagram showing a conventional example of a subfield configuration, which is an example of the address/display separation system widely used in the current PDP apparatus. As shown schematically, one frame is made up of n subfields SF1-SFn. Each subfield has a reset period R, an address period A, and a sustain period S. During the reset period R, the charges formed during the sustain period in the immediately preceding subfield are erased (or reduced) and, at the same time, the charges are rearranged in order to support a discharge during the following address period, and all of the cells are brought into a substantially uniform state. During the address period A, an address discharge is caused to occur to determine cells to be lit and wall charges are formed in the cells to be lit in order to selectively cause a sustain discharge to occur. During the sustain period S, a sustain discharge is caused to occur repeatedly in the cells to be lit. The operations during the reset period R and the address period A are the same in each subfield. The display luminance is determined by the number of sustain pulses applied during the sustain period and in general the number of applied sustain pulses differs from subfield to subfield, but there may be a case where two or more subfields having the same or a similar number of sustain pulses, that is, two or more subfields having the same or a similar display luminance are provided in one frame. Moreover, as to how variously luminance-weighted subfields are arranged in each frame, various configurations have been proposed, but for the sake of simplicity, the following explanation is given on the assumption that subfields are arranged so that the luminance of a subfield is higher than that of the immediately preceding subfield. However, the present invention is not limited to the arrangement of subfields described above.
FIG. 3 is diagram showing a conventional example of drive waveforms in an address/display separation system three-electrode type PDP apparatus. During the reset period R, as shown schematically, in a state in which an on-cell reset voltage 87 is applied to the Y electrode, an on-cell reset obtuse wave 81, the voltage of which drops gradually, is applied to the X electrode, and thus the wall charges in a cell (a lit cell) in which a sustain discharge has been caused to occur in the preceding subfield are erased or reduced. This process is called the on-cell reset process. Next, in a state in which a write reset voltage 82 is applied to the X electrode, a write obtuse wave 88 is applied to the Y electrode to cause a discharge to occur in all of the cells, and thus the same wall charges are formed in the vicinity of the electrode. Moreover, in a state in which an adjusting voltage 83 is applied to the X electrode, an adjusting obtuse wave 89 is applied to the Y electrode to adjust the formed wall charges to a predetermined amount. Here, negative wall charges are formed in the vicinity of the Y electrode and positive wall charges are formed in the vicinity of the X electrode and in the vicinity of the address electrode. The reset process is described as above, and due to the reset process, all of the cells are brought into a uniform state. Although a predetermined amount of wall charges are left in all of the cells in order to make the process easier, during the following address period in the explanation described above, there are various examples of modifications such as one in which no wall charge is left.
There is a case where the process, in which the wall charges in a cell in which a sustain discharge has been caused to occur in the preceding subfield are erased or reduced, is included in the process during the sustain period, but it is assumed here, and in the following explanation, that the process in question is part of the process during the reset period. Either way, this process is performed between the sustain period and the reset period.
During the following address period A, in a state in which an X bias voltage 84 is applied to the X electrode and a Y bias voltage (non-selection potential) 90 is applied to the Y electrode, a scan pulse 91 having a voltage −Vs is applied to the Y electrode while the position of application is shifted sequentially and an address pulse 94 having a voltage VA is applied to the address electrode in the cells to be lit in synchronization with the scan pulse 91. Due to this, a large voltage VA+Vs is applied between the Y electrode and the address electrode in the cells to be lit, therefore, an address discharge is caused to occur therein. At this time, a large electric field is formed also between the X electrode and the Y electrode, therefore, an address discharge is caused to occur also between the Y electrode and the X electrode induced by the address discharge between the Y electrode and the address electrode. Because of the transition of the address discharge between the Y electrode and the address electrode to that between the Y electrode and the X electrode, wall charges having the polarity opposite to that of the voltage applied to the respective electrodes are accumulated in the vicinity of the Y electrode and the X electrode. These wall charges are used to selectively cause a subsequent sustain discharge to occur. It is assumed here that the X bias voltage 84 is Vx, the Y bias voltage (non-selection potential) 90 is a negative voltage −Vy, the voltage of the scan pulse 91 is −Vs, and the voltage of the address pulse 94 is VA. These voltages are set so that an address discharge is caused to occur in the cells to which the scan pulse 91 and the address pulse 94 have been applied simultaneously and no discharge is caused to occur in the other cells, and in the cells in which an address discharge has been caused to occur (in the lit cells), wall charges capable of selectively causing a subsequent sustain discharge to occur are formed in the vicinity of the X electrode and the Y electrode. The wall charges left in all of the cells at the end of the reset period will serve to cause an address discharge to occur without fail even if a voltage to be applied between the Y electrode and the address electrode by the scan pulse 91 and the address pulse 94 is small. The wall charges in the cells in which no address discharge has been caused to occur (the wall charges formed during the reset period) are retained until a subsequent discharge is caused to occur. Here, an example is explained, in which an address discharge is caused to occur in the cells to be lit and wall charges required to selectively causing a sustain discharge to occur are formed, but there may be a case where uniform wall charges are formed in all of the cells during the reset period and the wall charges are erased in the cells not to be lit by causing an address discharge to occur.
During the following sustain period, a sustain pulse 85 having the voltage −Vs is applied to the X electrode and a sustain pulse 92 having a voltage Vs is applied to the Y electrode. Due to this, a voltage 2Vs is applied between the X electrode and the Y electrode. In the cells in which an address discharge has been caused to occur, the voltage due to the wall charges formed by the address discharge is added to ZVs, therefore, the discharge start voltage is exceeded and a sustain discharge is caused to occur. In the cells in which no address discharge has been caused to occur, no sustain discharge is caused to occur. In the cells in which a sustain discharge has been caused to occur, wall charges having the opposite polarity are formed by the sustain discharge. Next, when a sustain pulse 86 having the voltage Vs is applied to the X electrode and a sustain pulse 93 having the voltage −Vs is applied to the Y electrode, in the lit cells in which a sustain discharge has been caused to occur, the voltage due to the wall charges having the opposite polarity formed by the sustain discharge is added and a subsequent sustain discharge is caused to occur, but no discharge is caused to occur in the unlit cells in which no sustain discharge has been caused to occur. As described above, because the application of a sustain pulse reverses the polarity of the wall charges to be formed, a sustain discharge is caused to occur continuously in the lit cells by applying a sustain pulse having the opposite polarity alternately to the X electrode and the Y electrode.
The luminance of a subfield is set by the number of sustain discharges. As shown in FIG. 3, two sustain discharges are caused to occur in SF1 and four sustain discharges are caused to occur in SF2, and in a subfield whose luminance is higher, the number of sustain discharges is further increased. As the period of a sustain pulse is constant, in general, the length of the sustain period is determined by the number of sustain discharges. By the way, in an AC type PDP, as two discharges that reverse the polarity make a pair, in general, the number of sustain discharges is increased by a factor of a multiple of 2.
Here, a discharge in a PDP is explained. A discharge for forming a predetermined amount of wall charges in all of the cells during the reset period, in other words, a discharge by the reset voltage 82 and the write obtuse wave 88 and a discharge by the adjusting voltage 83 and the adjusting obtuse wave 89 do not relate to a display and light emission caused by these discharges is the same in all of the cells, therefore, the contrast is reduced as a result. Although not shown in FIG. 3, there may be a case where an initialization discharge is caused to occur in all of the cells by applying a large voltage for initialization between the X electrode and the Y electrode, and in this case also, such a discharge does not relate to a display and the contrast is reduced as a result. It is therefore desirable that such discharges are as weak as possible. Because of this, an initialization discharge is not caused to occur, if possible. Moreover, a discharge for forming a predetermined amount of wall charges is reduced considerably in light emission intensity by using the above-mentioned obtuse wave.
A discharge by the on-cell reset process for erasing or reducing the wall charges in the cells lit in the preceding subfield during the reset period, in other words, a discharge by the on-cell reset voltage 87 and the on-cell reset obtuse wave 81 is a discharge that relates to the display in the preceding subfield. Moreover, an address discharge and a sustain discharge are charges that relate to a display.
Conventionally, as to the luminance of each field, only the light emission luminance due to a sustain discharge is considered in general. On the other hand, erasure of charges is performed by a discharge small in the intensity by using an obtuse wave, such as a discharge by the on-cell reset voltage 87 and the on-cell reset obtuse wave 81.
The quality of display of a PDP apparatus has been improved yearly, but improvement is still demanded and the improvement in displaying performance of low-luminance gradations is particularly demanded. Japanese Unexamined Patent Publication (Kokai) 11-65517 has described the necessity to consider the luminance by other discharges that relate to a gradated display, whereas only the light emission luminance by a sustain discharge is considered conventionally.
When a gradated display is produced in an AC type color plasma display by combining subfields of different luminance, the displaying performance of low-luminance gradations is determined by the luminance of a subfield having the lowest luminance. The above-mentioned Japanese Unexamined Patent Publication (Kokai) No. 11-65517 and Japanese Unexamined Patent Publication (Kokai) No. 2003-66897 have described a configuration in which subfields made up of only a reset period and an address period, without a sustain period, are provided.
FIG. 4 is a diagram showing a subfield configuration when a subfield having no sustain period is provided in a frame, and FIG. 5 is a diagram showing an example of drive waveforms in SF1 and SF2 in such a case. FIG. 5 shows an example, in which the configuration described in Japanese Unexamined Patent Publication (Kokai) No. 11-65517 and Japanese Unexamined Patent Publication (Kokai) No. 2003-66897 is applied to the drive waveforms in FIG. 3. As shown in FIG. 4 and FIG. 5, the SF1 has only the reset period R and the address period A. Due to this, the luminance of the SF1 can be reduced and the displaying performance of low-luminance gradations can be improved. As shown in FIG. 5, the operation during the address period in SF1 and the operation during the address period in SF2 are the same.